The present invention relates to the field of integrated circuits, and more specifically to techniques to reduce the utilization of external pins in implementing integrated circuit functionality.
Semiconductor technology continues to improve. This technology allows greater and greater functionality to be provided by a single integrated circuit or xe2x80x9cchip.xe2x80x9d Signals are input to and output from the chip using external pins or pads. The chip interfaces to external circuitry, possibly on other chips, using the external pins.
Many functions such as testing and configuration of an integrated circuit are performed using the external pins. An integrated circuit may be packaged in a package having a sufficient number external pins to bond to all the pads of the integrated circuit. However, it is also desirable that the same integrated circuit may be packaged or xe2x80x9cdownbondedxe2x80x9d into a smaller package with fewer external pins. Smaller packages may be desirable because of their reduced cost. For example, it is desirable to use a package size that provides a sufficient number of I/Os. And, a larger package size is not used because the additional I/Os would be left unused.
It is important that functions such as testing and configuration remain accessible even when the integrated circuit is downbonded into a smaller package. Consequently, there is a need for techniques of implementing functions in integrated circuits to facilitate downbonding of the integrated circuit into a package with fewer pins.
The present invention is a technique of implementing functionality on an integrated circuit to facilitate downbonding of the integrated circuit into packages with fewer pins. Furthermore, in a specific embodiment, the present invention is a technique to reduce the number of required test pins, especially for low-pin count packages. Downbonding is desirable since it provides the customer with a wide range of package choices and the option to get a low-pin count package of the same device for much lower price.
As a specific example, in a programmable integrated circuit such as a programmable logic device (PLD), test data may be serially input using a single test pin into the integrated circuit in serial for two (or more) columns of logic array blocks, instead of one column. Many columns may be input in parallel using a plurality of test pins.
Test data is input using the test pin, and is stored in a first register. This test data is then transferred in parallel to a second register. From the second register, the test data may be transferred to the logic array blocks for testing of the logic array blocks. The technique of the present invention will provide the same full test coverage of the device. With fewer number of test pins, the device can be downbonded to the smaller pin count packages.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.